1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having an element isolation structure.
2. Description of the Background Art
In manufacturing a semiconductor integrated circuit, an element isolation structure having an element isolation region is required for independently controlling each element without electrical interference between elements in operation. One well known method of forming an element isolation region is an LOCOS (Local Oxidation of Silicon) method, and various improvements have been employed.
As a first conventional method of manufacturing a semiconductor device, description will hereinafter be made on a method of forming an element isolation region disclosed in Japanese Patent Laying-Open No. 63-217639, and by T. Mizuno et al. in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 11, NOVEMBER 1987, pp. 2255-2259.
FIGS. 31 to 36 are cross sectional views sequentially showing the first conventional method of manufacturing the semiconductor device disclosed in the above prior art documents. Referring to FIG. 31, a silicon oxide film 303, a polycrystalline silicon film 305 and a first silicon nitride film 307 are formed sequentially in stack on the whole surface of a silicon substrate 301.
Referring to FIG. 32, a photoresist 321 is applied onto the whole surface of first silicon nitride film 307, and patterned in a desired configuration with photolithography or the like, so that a resist pattern 321 having a hole pattern 321a with an opening diameter L.sub.2 is formed. With resist pattern 321 as a mask, first silicon nitride film 307 and polycrystalline silicon film 305 are sequentially etched away until the surface of silicon oxide film 303 is exposed. As a result, an opening 309 is formed in first silicon nitride film 307 and polycrystalline silicon film 305, which passes through these two layers and whose diameter is substantially the same as the opening diameter L.sub.2. Thereafter, resist pattern 321 is removed.
Referring to FIG. 33, a second silicon nitride film 313a is formed on the surface of silicon oxide film 303 and first silicon nitride film 307 so as to cover an inner wall of opening 309. Anisotropical etching is effected on second silicon nitride film 313a.
Referring to FIG. 34, through this etching, a sidewall nitride film 313 is formed on the surface of silicon oxide film 303 so as to be left only at the sidewall of opening 309.
Referring to FIG. 35, silicon substrate 301 is selectively subjected to thermal oxidation process with sidewall nitride film 313 and first silicon nitride film 307 as a mask, to form an element isolation oxide film 315 at the bottom of opening 309. Thereafter, sidewall nitride film 313, first silicon nitride film 307, polycrystalline silicon film 305 and silicon oxide film 303 are sequentially etched away, resulting in the state shown in FIG. 36.
Japanese Patent Laying-Open No. 63-217640 discloses a method of forming an element isolation oxide film having a higher electrical isolation effect with the similar process as the above-described one, wherein on a silicon substrate formed is a groove within which an element isolation oxide film is formed. This method will hereinafter be described as a second conventional method of manufacturing a semiconductor device.
FIGS. 37 to 44 are cross sectional views showing in sequence the steps of the second conventional method of manufacturing the second conventional semiconductor device disclosed in the above publication. Referring to FIG. 37, a first silicon oxide film 403, a polycrystalline silicon film 405 and a first silicon nitride film 407 are formed sequentially in stack on the whole surface of a silicon substrate 401.
Referring to FIG. 38, a photoresist 421 is applied on the whole surface of first silicon nitride film 407, and patterned in a desired configuration by photolithography or the like to form a resist pattern 421. With resist pattern 421 as a masks first silicon nitride film 407 and polycrystalline silicon film 405 are sequentially etched away until the surface of first silicon oxide film 403 is exposed. Through the etching, a first opening 409a is formed passing through first silicon nitride film 407 and polycrystalline silicon film 405.
Referring to FIG. 39, first silicon oxide film 403 and silicon substrate 401 are sequentially etched away with resist pattern 421 being left. Through the etching, a second opening 409b passing through first silicon oxide film 403 and having a prescribed depth from the surface of silicon substrate 401 is formed. First and second openings 409a and 409b constitute an opening 409. Thereafter, resist pattern 421 is removed.
Referring to FIG. 40, the surface of silicon substrate 401 and polycrystalline silicon film 405 which is exposed at opening 409 is lightly oxidized by an oxidizing atmosphere, to form a second silicon oxide film 411 on the outer periphery of opening 409. Second silicon oxide film 411 relaxes a stress between silicon substrate 401 and a sidewall nitride film to be formed in a later process, in thermal oxidation process.
Referring to FIG. 41, a second silicon nitride film 413a is formed on the surface of second silicon oxide film 411 and first silicon nitride film 407 so as to cover the inner wall of opening 409. Subsequently, second silicon nitride film 413a is anisotropically etched back.
Referring to FIG. 42, through this etching, a sidewall nitride film 413 is formed on the surface of second silicon oxide film 411 so as to be left only at the sidewall of opening 409. With sidewall nitride film 413 and first silicon nitride film 407 as a mask, silicon substrate 401 is selectively subjected to thermal oxidation process.
Referring to FIG. 43, through the thermal oxidation process, an element isolation oxide film 415 is formed at the bottom of opening 409. Sidewall nitride film 413, first silicon nitride film 407, and first and second silicon oxide films 403 and 411 are sequentially etched away, resulting in the state shown in FIG. 44.
In the second conventional method of manufacturing the semiconductor device described above, second opening 409b having a prescribed depth from the surface of silicon substrate 401 is formed in the step shown in FIG. 39. At the bottom of second opening 409b element isolation oxide film 415 is formed. Element isolation oxide film 415, as shown in FIG. 44, is thus buried in a deeper region (in the direction of depth) than element isolation oxide film 315 shown in FIG. 36 from the upper surface of silicon substrate 401. Therefore, when elements are formed on both sides of element isolation oxide film 415, electrons must move between the elements around element isolation oxide film 415 through a region thereunder, which enhances the electrical isolation effect on element isolation oxide film 415 compared to element isolation oxide film 315.
The height from the upper surface of silicon substrate 401 up to the upper surface of element isolation oxide film 415 is reduced by the downwardly buried (in the direction of depth) amount of element isolation oxide film 415, so that the surface of silicon substrate 401 is well-planarized. Accordingly, when a gate electrode or an aluminum wiring is to be formed thereon, patterning thereof can be performed easily.
In the first and second conventional methods of manufacturing the semiconductor device, the polycrystalline silicon film is formed between the first silicon oxide film and the first silicon nitride film. Since the polycrystalline silicon film has a higher oxidation rate compared to a silicon nitride film, oxidation in a longitudinal direction (the direction of film thickness) is dominant, while oxidation in a lateral direction is suppressed, whereby formation of a bird's beak is suppressed. Such suppression of a bird's beak by the polycrystalline silicon film is described in Tech. Dig. Int. Electron Device Meeting 1980 pp. 565-568.
The following two problems arise in the first and second conventional methods of manufacturing the semiconductor device.
A first problem is that the thickness of first silicon nitride film 307 is reduced in etchback of second silicon nitride film 313a shown in FIG. 33, causing a bird's head and a bird's beak. Detailed description thereof will be hereinafter given with respect to the first conventional manufacturing method as an example.
In the first conventional method of manufacturing the semiconductor device, opening 309 is formed in silicon nitride film 307 and polycrystalline silicon film 305 with resist pattern 321 patterned by photolithography or the like as a mask, in the step shown in FIG. 32. The diameter L.sub.2 of opening 309 is thus determined by resolution of the photolithography. Specifically, the opening diameter L.sub.2 is 0.3 .mu.m in the minimum processed dimension by photolithography utilizing an excimer laser beam, and cannot be made smaller than 0.3 .mu.m by photolithography. Accordingly, sidewall nitride film 313 is formed in the step shown in FIG. 34, by which the dimension L.sub.2b of silicon oxide film 303 exposed out of sidewall nitride film 313 can be made smaller by the width L.sub.2a of sidewall nitride film 313 than the minimum processed dimension L.sub.2 (approximately 0.3 .mu.m) by photolithography (L.sub.2b =L.sub.2 -(2.times.L.sub.2a)). Since the dimension L.sub.2b of the exposed surface of silicon oxide film 303 can be made smaller than the minimum processed dimension by photolithography, a miniaturized element isolation oxide film can be formed, which will meet a requirement for miniaturization.
Sidewall nitride film 313, however, is formed by etchback of second silicon nitride film 313a as shown in FIGS. 33 and 34. In this etchback, second silicon nitride film 313a is usually overetched by approximately 20 to 30% of its thickness. Therefore, first silicon nitride film 307 is also etched away together with second silicon nitride film 313a, so that the thickness of first silicon nitride film 307 is reduced. Particularly, with regard to miniaturization of elements, the thickness of first silicon nitride film 307 is considered to be significantly reduced. When thermal oxidation process is performed for forming element isolation oxide film 315 with the thickness of first silicon nitride film 307 being small, the length of a bird's beak 315b is increased as shown in FIG. 45.
This is expressed by the following relation between a thickness tn of first silicon nitride film 307 and a bird's beak amount L.sub.b, described by N. Guillemot et al., in IEEE Electron Device, ED-34, 1034 (1987): ##EQU1## where T.sub.OX indicates an oxidizing temperature, t.sub.OX indicates a thickness of a pad oxide film, and KL is a constant.
The experimental data thereof is described by T. Mizuno et al., in IEEE Transactions on Electron Devices, VOL. ED-34, No. 11, November 1987, pp. 2255-2259.
The fact that the smaller thickness of first silicon nitride film 307 results in the larger bird's beak amount L.sub.b can be explained as follows. Referring to FIG. 45, when the thickness of first silicon nitride film 307 is reduced, flexural rigidity thereof is reduced, so that first silicon nitride film 307 may easily lift up. As a result, an oxidation species tends to be introduced between silicon oxide film 303 and polycrystalline silicon film 305 and between silicon oxide film 303 and silicon substrate 301. Polycrystalline silicon film 305 is thus considerably oxidized to cause a bird's head, and silicon substrate 301 is also oxidized to increase the bird's beak.
Referring to FIG. 46, a width W.sub.2a of element isolation oxide film 315 thus formed is increased by the length of bird's head and bird's beak 315b. As a result, in spite of provision of sidewall nitride film 313 for forming a miniaturized element isolation oxide film, the thickness of silicon nitride film 307 is decreased, whereby miniaturization cannot be accomplished.
Also in the second conventional manufacturing method, a width W.sub.3a of element isolation oxide film 415 is increased by the length of bird's head and bird's beak 415b as shown in FIGS. 48 and 49 for the above reason.
A second problem is that a defect is introduced into silicon substrate 301 in thermal oxidation, thereby lowering a junction breakdown voltage thereof, which will be described in detail with respect to the first conventional manufacturing method.
Referring to FIG. 34, in the first conventional method of manufacturing the semiconductor device, silicon oxide film 303 is formed to have the thickness of approximately 150 .ANG.. In general, thermal expansion coefficients of silicon substrate 301 and sidewall nitride film 313 are significantly different. Therefore, when sidewall nitride film 313 is directly formed on silicon substrate 301 without interposing silicon oxide film 303 therebetween, a defect or a stress might be introduced into silicon substrate 301 due to heat applied in thermal oxidation. In order to prevent this, silicon oxide film 303 is interposed between silicon substrate 301 and silicon nitride film 303, as shown in FIG. 34. Silicon oxide film 303 serves as relaxing a stress caused by the difference of the thermal expansion coefficients.
However, when a ratio T.sub.O2 /T.sub.N2 of a thickness T.sub.O2 of silicon oxide film 303 to a height T.sub.N2 of sidewall nitride film 313 is smaller than a prescribed value, silicon substrate 301 cannot relax the stress completely, whereby a defect 317 or a stress may be introduced into silicon substrate 301 in the vicinity of an edge of isolation oxide film 315 in thermal oxidation, as shown in FIG. 45. This is described by A. Bohg et al., in Appl. Phys. Lett. 33 (10), 15 Nov. 1978, p. 895.
Such introduction of defect 317 or a stress into silicon substrate 301 leads to distribution of defects 317 over a p-n junction portion including p-type silicon substrate 301 and an n-type impurity region 319 formed on either side of element isolation oxide film 315, as shown in FIG. 47. In this case, the junction breakdown voltage might be reduced because of current leakage through defects 317 distributed over the junction portion.
However, if the thickness of silicon oxide film 303 is increased in order to increase a ratio T.sub.O2 /T.sub.N2 of the thickness T.sub.O2 of silicon oxide film 303 to the height T.sub.N2 of sidewall nitride film 313 larger than a prescribed value, the amount of a bird's beak would be increased.
Also in the second conventional manufacturing method, defect 317 or a stress may be introduced, for the same reason as above, into silicon substrate 401 around an edge of isolation oxide film 415a as shown in FIGS. 48 and 49, thereby causing current leakage in a p-n junction portion of p-type silicon substrate 401 and an n-type impurity region 419, as shown in FIG. 50, so that the junction breakdown voltage thereof is decreased.
Also in this case, if a thickness T.sub.O3 is increased in order to increase a ratio T.sub.O3 /T.sub.N3 of the thickness T.sub.O3 of second silicon oxide film 403 to a height T.sub.N3 of sidewall nitride film 413 larger than a prescribed value as shown in FIG. 42, the amount of a bird's beak would be increased. More specifically, second silicon oxide film 411 is formed through oxidation. Polycrystalline silicon film 405 and silicon substrate 401 are at this time oxidized by the thickness T.sub.O3 from the sidewall of opening 409 toward the outer periphery (as indicated by the arrow R). If thermal oxidation is performed with polycrystalline silicon film 405 and silicon substrate 401 oxidized by a large thickness at the outer periphery of opening 409, the length W.sub.3a of element isolation oxide film 415 will be increased by the thickness T.sub.O3 toward the outer periphery of opening 409, as shown in FIG. 49. Accordingly, the thickness of second silicon oxide film 403 cannot be increased in the step shown in FIG. 40.
As described above, simple provision of frames 313 and 413 for thermal oxidation does not contribute to miniaturization of element isolation oxide films 315 and 415 against its purpose, and decreases electrical reliability of the element isolation structure.
Referring to FIG. 51, when second silicon oxide film 411 is formed on the inner wall surface of opening 409 through thermal oxidation, an oxidizing agent cannot easily enter a corner portion (a region C) of opening 409. The corner portion is hardly oxidized because of its high stress and suppressed oxidation rate. As a result, when sidewall nitride film 413 is formed as shown in FIG. 42, the thickness of the oxide film on the lower side of sidewall nitride film 413 is small, so that a defect tends to be introduced into silicon substrate 401 in a heat treatment with sidewall nitride film 413 as a mask. Therefore, the above-described reduction in the junction breakdown voltage will be promoted when second silicon oxide film 411 is formed on the inner wall of opening 409 by thermal oxidation.